How Many Bits In Each Register Risc V

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RISCV didactics set explanation

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V1.0	2020/11/27	Initial Release

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Content

ane. General-Purpose Annals and PC

2. RISC-V base instruction formats

3. I-type

4. U-blazon

5. R-blazon

half-dozen. J-blazon

7. B-type

eight. Load & Store

9. Accost alignment

10. Handle overflow situations

1. General-Purpose Register and PC

The CPU contains 32 general-purpose registers, sometimes they are called general-purpose register files. Equally shown in Figure 1-ane, the full general-purpose registers are named X0-X31, the value of the first register X0 is always 0, and the registers X1-X31 are readable and writable. There are 32 General-Purpose registers in total. The number 0-31 behind X0-X31 is called the alphabetize. The alphabetize can besides be understood every bit the address of the register. When an didactics needs to use the General-Purpose Registers, The registers can be found by the index. The following chapters volition have a defended FPGA program to organize the reading and writing of register files. For a 32-bit arrangement, the width of all full general-purpose registers is 32bit.

PC (programme counter) is the program counter and as well a register. Within CPU, the PC register is not put together with the above 32 general-purpose registers, and the PC is non included in the register file. The value of XLEN is generally related to the CPU architecture. If information technology is a 32-bit compages CPU, and so the value of XLEN is 32. In Effigy i-ane, XLEN-i = 32-1 = 31, which means that the highest bit in a general-purpose register is 31. In a 64-bit CPU, the width of the general-purpose register is 64, and the width of the PC is also 64 bits, the highest fleck is 63.

Figure1-1 Full general-Purpose Register and pc structure diagram

2. RISC-5 base of operations didactics formats

RV32I can be divided into vi basic instruction formats. R-type instructions for register-register operations, an I-blazon instructions for immediate and load operations, and S-type instructions for store operations. B-type instructions for conditional branch operations. U-type instructions for long firsthand and J-type instructions for unconditional jumps.

Figure 2-1 Assembly educational activity auto lawmaking format

R-type：

R-blazon is an operation without immediate. The immediate is the number that exists as an integer in the instructions. The binary format of the R-type assembly educational activity machine code is shown in Figure ii-1. The length of a binary instruction is 32bit. The seven $.25 from 0 to vi are opcode (operation code), used to identify the type of pedagogy. $.25 7 to eleven are the index of the rd register. The Rd annals is also called the destination register, and the destination annals is the register used to store the consequence. rs1 and rs2 are called source registers. In most cases, instructions demand to read the values of the two source registers for operations. The alphabetize of rs1 is in bits 15-19, and the alphabetize of rs2 is in bits 20-24. The following is an example of how to employ the register index.

Example: When the value of the position index of rd in the instruction is v'b00011, which is 3 in decimal notation. Afterward the CPU receives this instruction, it volition detect that the value of the vii-11bit position is 3, and it will find the X3 register as the rd register in the 32 general-purpose registers, and finally write the result to the x3 register. If the index of rs1 and rs2 is 2 and 4 at the position of flake 15-nineteen and bit xx-24 in the binary associates instruction at this time, the CPU will detect that the value of the corresponding position of rs1 and rs2 in the educational activity is 2 and iv, then x2 and x4 are found in 32 General-Purpose Registers. Read values from registers x2 and x4 and perform operations.

This teaching requires opcode plus funct3, and sometimes funct7 together to determine the type of operation that this instruction allows the CPU to perform.

R-blazon：

The R-type command format is very clear. In the actual encoding procedure, the arrangement of encoding positions is meaningful. For example, the encoding position of the iii register indexes in different instruction formats are always the same. Index of Rd is at 11-7, Index of rs1 is at 19-xv, and Alphabetize of rs2 is at 24-20. This is their fixed position. Some instructions may not exist useful. The index to the partial register. For case, there is no rs2 in the second instruction type I-type, but there are rs1 and rd and their indexes are in the corresponding positions. For another case, in s-type funct3 is at bits 14-12. The opcode is available in all pedagogy formats, and the position remains unchanged, always scrap 0-6.

I-type：

The upper 12 bits of I-type is an immediate number. The opcode is different from other education formats because the corresponding specific operations are unlike, and other parts are very similar to R-type.

South-type：

The characteristic of S-type instruction is that there is no rd register. In this type of pedagogy, the firsthand is divided into 2 parts, the first part is in bit11-5, and the 2nd part is in bit4-0. The 5 $.25 of the immediate four-0 occupy the position of rd in other educational activity formats, and 5-11 occupy the position of funct7. Explain that the command format does not need to write back. That is, read the two values from the 2 registers and perform the operation together with the immediate, and write the event to the annals after the operation is over.

U-Blazon

A 20-chip immediate is provided in the U-type pedagogy. The final operation effect is related to the xx-bit immediate, and the result is written dorsum to the rd register. The opcode determines the blazon of operation. There are no funct3, rs1, rs2, and funct7 in U-type. This blazon of instruction structure is very elementary.

B-Type

B-blazon instructions are mainly used every bit branch instructions, but they are conditional Branch. It means to make up one's mind whether to jump or not need to depend on whether the condition is valid. The B-type motorcar code structure is shown in Effigy 2-one. The instruction does not include rd register and funct7, but contains rs1, rs2, funct3 and immediate. The immediate is divided into two areas. The encoding of B-type instruction immediate is out of gild. The reason is not described in item here. In that location is a specific article on the official site explaining why information technology is out of order. In short, it has been verified that the effect on CPU performance function when the immediate number sequence is in this order is very well. Only the firsthand is disrupted, so it will be decoded when the CPU executes in the future. Afterwards decoding, the CPU needs to restore the disrupted immediate in lodge. For example, when the CPU gets a B-blazon instruction, the immediate in it is scrambled, and the CPU needs to arrange the immediate in the order of 12-i to restore the firsthand.

J-Type

The format of this pedagogy is very similar to U-blazon, it simply accept Rd register and immediate and opcode. At the aforementioned time, the immediate of J-type is also disrupted. That ways that the CPU must commencement put the firsthand numbers together to restore the original immediate numbers when decoding.

3.I-type

Figure3-ane I-blazon format

There are 15 instructions in total for I-type. At present innovate the first half dozen instructions. Please refer to Figure three-i for I-type command format. The opcode corresponding to the I-type instruction is named OP-IMM. Information technology means firsthand operation code (IMM: immediate).

The firsthand opcode OP-IMM==7'b001_0011. When opcode==OP-IMM==7'b001_0011, it proves that the instruction is an I-type instruction, and the specific behavior of this education is determined by the value of funct3.

The following office describes the instructions in I-blazon i by 1.

ADDI：ADDI rd,rs1,imm[11:0]

Add stands for addition, I stands for immediate, and the ADDI instruction means addition with firsthand. This instruction adds the value in the rs1 register to the immediate, and and so stores the result of the addition in rd. ADDI corresponds to funct3 == 3'b000, which means that funct3==iii'b0000 in the I-type instruction means that the didactics is an ADDI instruction.

A new concept pseudo-instruction is introduced here, taking the MV pedagogy as an example.

MV：MV rd,rs1

MV (move) pedagogy. This teaching is to move the value in rs1 to rd. There is a move instruction in x86 and besides in mcs51. What are pseudo instructions? Pseudo instructions are instructions that do not exist in the associates didactics fix. These instructions are convenient for assembly programmers and are oft used. For example, in the assembly program, there are often shifts between registers. Then the MV instruction is often used. Take the MV didactics as an case, its bodily significant is ADDI rd, rs1,0. That is to say, the value in the rs1 register is added upwardly with the immediate 0 , and finally stored in the rd register. Because the value of rs1 does not change after rs1 is added to zero, the MV instruction moves the value of rs1 to rd. The developer can write such a pseudo-educational activity MV when writing the assembler. The compiler software will interpret this instruction into ADDI rd, rs1, 0 when the program is compiled, so send the ADDI instruction to the CPU to run.

SLTI：SLTI rd,rs1,imm[xi:0]

In the second instruction SLTI, S stands for Set up, and its role is to fix rd. Set the value in the rd register to 0 or i. It should be noted that in the instruction, if the condition is satisfied, the flake is set up to 1, and if the status is not satisfied, the bit is set to 0. The setting condition of this didactics is LT: less than. I stands for immediate. Then the judgment status is whether the value of rs1 is less than the firsthand. Because the rs1 register is 32-bit in all operations, and the immediate in this didactics is 12-bit, the firsthand must be expanded starting time, and and then the operation volition be performed after the expansion. Annotation that the extensions here are all signed extensions.

Hither is an example to explain the signed extension. For case, in that location is a 12-scrap immediate. If the highest bit is 0, information technology means that the immediate is positive. If the highest bit is 1, it means that the immediate is negative. When the positive number is sign-extended, the upper 20 bits are all filled with 0, and when the negative number is sign-extended, the upper 20 bits are all filled with i.

SLTIU：SLTIU rd,rs1,imm[xi:0]

In the instruction SLTIU, U represents an unsigned number. It means to set after comparing unsigned numbers.

Instance: Compare 8-fleck binary numbers. -1: 8'b1111_1111, -2:8'b1111_1110. When compared as a signed number, -2<-1, if it is used as an unsigned number, the comparison is still valid, but if you use -ii and +ane 8'b0000_0001 to compare an unsigned number. At this time, 1111_1110>0000_0001. (254>1)

Pseudo-instruction SEQZ：SEQZ rd,rs1 (SLTIU rd,rs1,ane)

If rs1==0, and so rd is ready to 1.

This pseudo-instruction is a special case of SLTIU and volition be used frequently.

ANDI: ANDI rd,rs1,imm[11:0]

The immediate is expanded to 32 bits every bit a signed number, then perform AND with rs1 afterwards the extension, and store the result in rd.

ORI: ORI rd,rs1,imm[eleven:0]

The immediate is expanded to 32 bits as a signed number and do OR with rs1. The effect is written into rd.

XORI: XORI rd,rs1,imm[eleven:0]

The firsthand is expanded to 32 bits as a signed number and do XOR with rs1. The result is written to rd.

The format reflects the flexibility of instructions. The format does not mandate which register rs1 and rd are, and programmers need to select registers from 32 full general-purpose registers when writing associates programs.

Pseudo-pedagogy Non：NOT rd,rs1 (XORI rd,rs1,12'hfff)

Not is a negation teaching. The role is to reverse the value in rs1 and store it in rd. It will be translated into (XORI rd,rs1,12'hffff)

The assembly educational activity format and corresponding funct3 are shown in Figure 3-ii below

Figure3-2 some I-blazon assembly instructions and funct3 machine code

Shift instruction

Figure3-3 Shift educational activity

SLLI rd,rs1,shamt[four:0]

SLLI ：shift left logical past shamt(shift corporeality) ，The number of shifts is determined by imm "4:0". This instruction ways to shift the value of rs1 to the left in shamt[4:0], use 0 to fill the low bits of rs1, and write the result to Rd.

2. SRLI rd,rs1,shamt[4:0]

SRLI：shift right logical .Shift the value in rs1 to the right by shamt[4:0] $.25, add nix to the high bits of rs1, and write the result to rd.

3. SRAI rd,rs1,shamt[iv:0]

SRAI：Arithmetic shift right, shift the value in rs1 to right by shamt[4:0] bits, the loftier bits of rs1 are filled with the original rs1[31], and the upshot is written into rd.

Notation that the OP-IMM and funct3 codes of SRLI and SRAI are the aforementioned. The divergence is the instruction by the value of imm[xi:v], as shown in Figure 3-iii

iv. U-blazon

Figure4-1 U-type instruction machine code format

type instructions include opcode, rd, 20-flake firsthand. As shown in Figure four-ane.
LUI rd,U_imm

LUI is identified past opcode. The opcode name is LUI and the value is 7'b011_0111. This didactics writes U_imm into the loftier 20 bits of rd, and the depression 12 bits of rd volition be filled with 0.

AUIPC rd,U_imm

AUIPC is identified by opcode, the opcode name is AUIPC, and the value is 7'b001_0111. The instruction is to place the xx-scrap immediate in the high 20 bits of the 32-bit, and add the depression 12 to the current PC and write it into the rd register. PC is the program counter.

The above 2 instructions can form a high 20-bit beginning. With JAL, JALR, and conditional jumps, whatsoever spring in the 32-chip space can exist accomplished.

We will innovate JAL, JALR, and conditional jumps in subsequent chapters.

5. R-blazon

Figure5-1 R-blazon instruction auto lawmaking format

At that place are x R-type instructions in full. The opcode proper noun is OP and the value is 7'b011_0011. Small instructions are adamant according to funct3, and if information technology is not plenty, funct7 is used to determine. Equally shown in Figure five-1, information technology can be plant that it is similar to the immediate instruction.

i.ADD rd,rs1,rs2

addition

funct7==vii'b0000000;

funct3==iii'b000;

This instruction writes the result of rs1+rs2 into rd, ignoring overflow (overflow can be handled by software).

2.SLT rd, rs1,rs2

Funct7==seven'b0000000;

funct3==3'b010 ;

rs1 and rs2 are compared with signed numbers, if rs1<rs2, rd is set up to 1, otherwise it is set to 0

3.SLTU rd,rs1,rs2

Funct7==7'b0000000;

funct3==iii'b011 ;

Use the unsigned number to compare rs1 and rs2, if rs1<rs2, rd is set to 1, otherwise it is set to 0

4.AND rd,rs1,rs2

funct7==seven'b0000000；

funct3==iii'b111;

Write the result of rs1&rs2 into rd, where & means that rs1 and rs2 are AND together fleck by bit

5. OR rd, rs1,rs2

funct7==seven'b0000000,

funct3==3'b110

Write the upshot of rs1|rs2 into rd, where | ways or

vi. XOR rd,rs1,rs2

funct7==7'b0000000,

funct3==three'b100 ;

Write the upshot of rs1^rs2 to rd, where ^ ways rs1 XOR rs2 fleck past flake

7. SLL rd,rs1,rs2

Logical shift left

Funct7==7'b0000000,

Funct3==3'b001;

Shift rs1 logically to the left according to the number specified in the lower 5 bits of rs2, fill in the lower bits with zeros, and write the result to rd

eight. SRL rd, rs1,rs2

Logical shift correct

Funct7==7'b0000000,

funct3==three'b101 ;

rs1 is logically shifted to the right according to the specified number of low 5 bits in rs2, and the high bits of rs1 are filled with zeros, and the result is written into rd

9. SRA rd,rs1,rs2

Arithmetic shift right

Funct7==vii'b010_0000,

funct3==3'b101 ;

Arithmetic shift rs1 to the right according to the specified number of low v $.25 in rs2, the loftier chip is adamant by the original rs1[31], and the result is written into rd. Annotation: When shifting, just the value of RS1 is copied to the temporary variable for shifting, and the original value remains abiding.

10. SUB rd,rs1,rs2

Subtraction

funct7==7'b010_0000,

funct3==three'b000;

Write the effect of rs1-rs2 to rd, ignore overflow (overflow can be handled by software)

The only difference between add-on and subtraction instructions is funct7

Add-on funct7==vii'b000_0000

Subtraction funct7==vii'b010_0000

vi. J-blazon

Figure6-i J-type instruction machine code format

Figure half-dozen-2 J-blazon diagram of firsthand recovery

JAL jump and link

JAL rd, label

opcode==7'b110_1111

Unconditional spring and link instructions

Use J-type format

Save the address of the next instruction (PC+iv) to the rd register, then set the PC to the electric current value plus the sign bit extension showtime. The default Rd register is x1. The characterization is an address label, programmer can proper name the label. It is essentially an address. Label is the accost where JAL pedagogy jumps to.

The arrangement of immediate seems a scrap messy, this is considering the primary purpose is to keep the position of opcode, rd , some firsthand aforementioned equally other educational activity formats.

Immediate recovery: inst[31], as shown in Figure half-dozen-2, inst[19:12] in the figure represents the position of the firsthand in the instruction, and so the encoding and decoding are strictly consistent. The encoding is done by the instruction compiler, and the decoding is done past the hardware circuit of the CPU. The post-obit capacity will introduce the RTL implementation of RISC-V. Notation that the depression chip is filled with 0 when restoring immediate.

The 20-chip immediate is an integer multiple of ii, which is added to the PC afterwards sign extension, imm[31:0]+PC forms an showtime, and the addressing range is ±1M

Rd=PC+iv rd is the link register

Examples and explanations of the compilation procedure:

Example: There is currently an associates instruction SUB x8, x3, x5, which should be converted into the binary format of the assembly instruction. sub determines that the opcode is 011_0011. If rd is x8, the position of rd in the binary code is 01000. The value of sub at the funct3 position is 3'b000. rs1 is x3, the value of the corresponding position is 00011, rs2 is x5, and then 24:xx is 00101. Finally, SUB educational activity fills 010_0000 in the funct7 position.

Note that the underscore in the number itself has no meaning, just for the convenience of users to read, for example, 0000_0001 is equal to 00000001.

Before jumping in the Jal instruction, the PC value needs to be compared with the address marked past the label, and the divergence is stored in imm. When jumping, imm+PC forms an kickoff, and the range is +-1M (xx bits). At the same time, save the current PC value +iv to rd.

Question: Why does the PC add 4?

Answer: There is a difference of iv between the addresses of the storage units in the education storage space (corresponding to 32 $.25 and 4 bytes). Adding 4 means that the address of the adjacent teaching is stored in the rd annals.

JALR

Spring and Link register

Note that JALR use I-type format

opcode==7'b110_0111

funct3==iii'b000

JALR rd,rs1,imm[11:0]

rd=PC+iv rd

As a link register, generally use annals x1 or register x5.

The 12-bit immediate is extended by the sign flake and added to the value of rs1, and the lowest bit of the result is set to zero to form a jump offset.

JAL and JALR can form a pair of instructions to complete the function call and return.

For example, there exist a command jal x1, 80000040, when running this command, rd is x1. Shop pc+4 in x1. The program jumps to the address 0x80000040 and runs. When this part of program is over, y'all need to use the command jalr x2, x1, 0x0; jump back, then cull x1 as rs1 in the jalr command. Now the immediate is 0, if the immediate is not nothing, yous need to change Afterwards firsthand is expanded, it is added to x1 to get a value as an address, and the programme jumps to this address. In full general, jal and jalr form a pair of instructions to consummate the function call and return.

7. B-type

Figure7-ane B-blazon Instruction car code format

B type instruction, B: branch educational activity. These jump instructions are conditional.

There are half dozen conditional spring instructions, as shown in Figure 7-ane

Opcode==7'b110_0011

BEQ rs1,rs2,characterization //(imm)

funct3==3'b000

Imm is a 12-bit immediate, which is an integer multiple of 2, sign extended to 32bit

Didactics function: If rs1==rs2, the jump offset is PC+imm, and the jump range is ±4K

Note that the feature of this pedagogy is that there is no rd, so the instruction does not record the current PC value before jumping.

As shown in Figure 7-i, it can be found that the firsthand in the educational activity does non take the 0th flake. Therefore, if the instruction jumps, it will jump at to the lowest degree 2 steps, for example, it can jump to 0x80000002 or 0x80000004, just non to 0x80000001 or 0x80000003. 1 address corresponds to 1 byte == 8bit space, because the shortest instruction of RISC-V is a 16-bit compressed instruction set, the default jump is 16bit==2byte , and the lowest fleck is 0 by default.

Besides note that the actual size of immediate later on adding 0 is thirteen bits, and the highest fleck imm [12] is the sign bit. If the highest bit is 0 then jump backward, if the highest bit is 1 then bound forward. Spring range is 4K.

BNE rs1,rs2, label

label==PC+imm[12:i]

funct3==iii'b001

If rs1!=rs2, the leap beginning is PC+imm, and the leap range is ±4K

BLT rs1,rs2, label

Funct3=iii'b100

First exercise signed comparing If rs1<rs2, the jump offset is PC+imm, and the jump range is ±4K

BLTU rs1,rs2, label ;

—label==imm[12:one]

funct3=iii'b110

Commencement do unsigned comparison, if rs1<rs2, the jump commencement is PC+imm, and the jump range is ±4K

BGE rs1,rs2, label ;

—label==imm[12:1]

funct3=3'b101 //GE — cracking or equal

Start do Signed comparing, if rs1≥rs2, the leap offset is PC+imm, and the jump range is ±4K

BGEU rs1,rs2, label;

—label==imm[12:1]

funct3=3'b101

Offset do unsigned comparison, if rs1≥rs2, the jump outset is PC+imm, and the bound range is ±4K

8. Load & Shop

Figure8-i LOAD instruction auto lawmaking format (I-type)

The instructions that mentioned earlier are all register instructions, and LOAD & STORE are instructions of the retention. In the load role, the value must be obtained from the memory, such as ROM, EPROM, EEROM, Flash, DDR, SRAM, and other memory.

There are 15 instructions for I-type, five instructions for LOAD

LW rd, starting time(rs1) ;

Fifty:load, w:discussion。Word 4byte or 32bit。

—showtime==imm[xi:0]

opcode==seven'b000_0011

funct3=3'b010

Read a copy of 32bit data from the retentiveness and store it in the rd register //LW —load word (32 bit)

The memory address is expanded by 12-bit immediate and added to rs1

LH rd,

LH H: one-half-word corresponds to 16bit

starting time(rs1);

—offset==imm[11:0]

opcode==vii'b000_0011

funct3=three'b001

Read the re-create of 16bit data from the memory and shop it in the rd register after sign bit extension //LH load one-half word

LHU rd, offset(rs1);

—offset==imm[xi:0]

opcode==seven'b000_0011

funct3=iii'b101

Read the copy of 16bit data from the retentiveness, expand past high fleck 0, and store it in the rd annals

LB rd, beginning(rs1)

opcode==7'b000_0011

funct3=iii'b000

Read a re-create of 8bit data from the memory, later on sign chip extension, shop it in the rd register

LBU rd, offset(rs1);

—beginning==imm[xi:0]

opcode==7'b000_0011

funct3=iii'b100

Read the copy of 8bit data from the memory, expand past high bit 0, and store it in the rd register

STORE

Figure8-2 Due south-type command format

The shop instructions use Due south-type format. The shop instruction writes the value to the memory, southward-type does not have rd.

Shop blazon include 3 instructions

opcode==seven'b010_0011

SW rs2, offset(rs1);

—offset==imm[11:0]

funct3=3'b010

Copy the value of rs2 to the memory, the accost calculation is the same equally the LOAD instruction

SH rs2, offset(rs1)

—offset==imm[11:0]

funct3=three'b001

Copy the value of the lower 16 bits of rs2 to the retention. The address calculation is the same equally the LOAD educational activity. The upper 16 bits are not needed and can be ignored.

SB rs2, offset(rs1)

—start==imm[xi:0]

funct3=3'b000

Copy the value of the lower 8 bits of rs2 to the memory, the address calculation is the aforementioned every bit the LOAD didactics.

ix.Address alignment

Equally mentioned earlier, the everyman bit of the jump instruction is automatically filled with 0 by default. This too represents data alignment. If it is 32bit data, the lower 2 $.25 of the address alignment are zero. This corresponds to the automated increase of iv to the PC value. Adding 4 in binary means adding 100, you can run across that the lower two bits are 00.

Question: Why does the lowest digit of the leap instruction default to 0 instead of the lowest digit of zero?

Respond: The current system is a 32-chip system. But the RISC-V didactics ready supports compressed instructions, that is, it supports a xvi-chip teaching gear up, and the information is 16 bits, then simply the everyman bit defaults to 0. RISC-Five has no viii-fleck education prepare.

For case, to read data from the memory, the first storage unit of measurement address is 0x80000000, the 2nd accost is 0x80000004

10. Handling of overflow situations

In the above chapter, it is mentioned that the ADD, ADDI, SUB and other three instructions may overflow in the calculation. The following examples show how to bargain with them.

RISC-V user transmission does non explain how to deal with the overflow situation, merely it is recommended to deal with it at the software level.

one. Unsigned number add-on overflow

ADD X5, X6, X7: x5=x6+x7 The addition of two unsigned numbers (actually positive numbers) cannot be smaller than the original value. If this happens, overflow has occurred, and the program needs to leap to the overflow treatment function Partial operation, BLTU x5, x6, overflow.

2. Add together signed numbers, but one of the operands is known to be a positive number,

The aforementioned judgment jump. Because a number plus a positive number cannot exist smaller than the original valuer.

ADDI x5,x6,+imm BLT x5,x6, overflow

three. Under normal circumstances, whether the number is positive or negative is not known at all. After adding, you need to gauge whether x7 is less than aught and tape it. slti x28,x7,0; When x7 is less than 0, the value of x28 is set to ane, which proves that x7 is a positive number. If x7 is negative, the value of x28 will exist set to 0. Instructions slt x29, x5, x6. Compare the values of x5 and x6 and store the result in x29. If x5 is less than x6. Then x29 is gear up to 1. Finally, if x28 and x29 are not equal, the overflow will overflow. Discuss in several situations.

A. Both x28 and x29 are i. Prove that x7 is negative and x29 is 1. Prove that x5 is less than x6. It is true considering calculation a negative number must increase and decrease

B. Both x28 and x29 are 0. X7 is a positive number, x5>=x6, plus the positive number gets bigger and bigger.

C. X28 is 1, and x29 is 0. It is impossible to increment by adding a negative number, so overflow occurs.

D. X28 is 0, x29 is 1, and it is impossible to subtract past adding a positive number, so overflow occurs.

As for the processing method, it is processed in the software according to the specific situation.

RISCV Instruction_Set_introduction_20201130